1. Field of the Invention
This invention relates to a differential amplifier circuit suitable for use with an internal voltage generation circuit used in a semiconductor integrated circuit device to produce a predetermined internal power supply voltage.
2. Description of the Related Art
A semiconductor integrated circuit device such as a semiconductor memory device in recent years does not directly use external power supply voltage VCC supplied from the outside, but lowers or raises external power supply voltage VCC by means of an internal voltage generation circuit to produce a predetermined internal power supply voltage and supplies the produced internal power supply voltage to internal circuits to achieve reduction of power consumption and augmentation of the reliability of the device.
In order to increase the storage capacity, for example, a semiconductor memory device employs memory cells of a refined transistor size. Since this makes it impossible to apply a high voltage to transistors, a lowered voltage power supply circuit is provided in the inside of the semiconductor memory device and supplies lowered voltage VINT lower than the external power supply voltage to the transistors for the memory cells.
Meanwhile, raised voltage VP higher than external power supply voltage VCC is sometimes applied to a word line of a DRAM, a non-volatile memory or a like device in order to assure a desired performance. Further, a semiconductor substrate is sometimes biased to a negative voltage in order to assure a high charge retaining characteristic of a DRAM. In this manner, a semiconductor memory device internally has an internal voltage generation circuit for producing various internal power supply voltages.
FIG. 1 is a block diagram showing an example of configuration of an internal voltage generation circuit.
Referring to FIG. 1, the internal voltage generation circuit includes raised voltage power supply circuit 10 for producing raised voltage VP, lowered voltage power supply circuit 20 for producing lowered voltage VINT , reference voltage generation circuit 30 for supplying predetermined reference voltage VREF to raised voltage power supply circuit 10 and lowered voltage power supply circuit 20, and comparison voltage generation circuit 40 for producing predetermined comparison voltage VR to be supplied to reference voltage generation circuit 30 in order to suppress reference voltage VREF from fluctuating because of a variation of the ambient temperature.
Raised voltage power supply circuit 10 includes comparator 11, ring oscillator 12 and charge pump 13 connected in series, and divides raised voltage VP output from charge pump 13 by means of resistors R1, R2 and feeds back divided voltage VP2 to comparator 11.
Comparator 11 compares divided voltage VP2 and reference voltage VREF with each other. If VP2 less than VREF, then comparator 11 outputs a High level as an enable signal, but if VP2  greater than VREF, then comparator 11 outputs a Low level as the enable signal.
Ring oscillator 12 includes a clock oscillator circuit and supplies a clock signal to charge pump 13 when the enable signal supplied from comparator 11 has the High level, but stops oscillation of the clock signal when the enable signal has the Low level.
Charge pump 13 produces raised voltage VP by multiple voltage rectification of the clock signal supplied from ring oscillator 12. If raised voltage VP rises higher than a predetermined voltage, then oscillation of ring oscillator 12 stops, and consequently, raised voltage VP drops gradually. On the other hand, if raised voltage VP drops lower than the predetermined voltage, then oscillation of ring oscillator 12 is restarted, and consequently, raised voltage VP rises. Raised voltage VP is maintained constant in this manner. As seen in FIG. 1, raised voltage VP is supplied to internal circuits of the semiconductor integrated circuit device and supplied also to lowered voltage power supply circuit 20 and reference voltage generation circuit 30.
FIG. 2 is a circuit diagram showing an example of configuration of the lowered voltage power supply circuit shown in FIG. 1.
Referring to FIG. 2, lowered voltage power supply circuit 20 includes output transistor 21 formed from an N-channel MOSFET supplied with external power supply voltage VCC for supplying lowered voltage VINT to an internal circuit serving as a load, differential amplifier circuit 22 supplied with raised voltage VP for outputting a control voltage for controlling the gate voltage of output transistor 21, and phase compensation capacitor CP interposed between an output contact of output transistor 21 and the ground potential for preventing oscillation of lowered voltage power supply circuit 20.
Differential amplifier circuit 22 includes transistors Q11, Q12 formed from P-channel MOSFETs connected commonly at the gates thereof, transistors Q13, Q14 formed from N-channel MOSFETs connected in series to transistors Q11, Q12 and connected at the respective sources thereof, and constant current source 23 for supplying predetermined current to transistors Q11 to Q14. Transistors Q11, Q12 form a current mirror circuit by connection of the gate and the drain of transistor Q11 so that values of Current flowing between the source-drain of transistors Q11, Q12 may be equal to each other.
Reference voltage VREF supplied from reference voltage generation circuit 30 is input to the gate of transistor Q13 connected to non-inverted input terminal 24, and the drain voltage of transistor Q14 which is an output of differential amplifier circuit 22 is applied to the gate of output transistor 21. Output voltage VINT (lowered voltage) output from the drain of output transistor 21 is fed back to the gate of transistor Q14 connected to inverted input terminal 25 of differential amplifier circuit 22.
Differential amplifier circuit 22 amplifies a difference between input voltages applied to inverted input terminal 25 and non-inverted input terminal 24 and outputs the amplified input voltage difference from the drain of transistor Q14. Accordingly, lowered voltage power supply circuit 20 shown in FIG. 2 operates so that, when output voltage VINT is lower than reference voltage VREF, the potential at node A of differential amplifier circuit 22 rises and source-gate voltage VGS of output transistor 21 increases, and consequently, output voltage VINT rises. On the other hand, when output voltage VINT is higher than reference voltage VREF, the potential at node A of differential amplifier circuit 22 drops and source-gate voltage VGS of output transistor 21 decreases, and consequently, output voltage VINT is lowered by the load. In other words, differential amplifier circuit 22 is controlled so that output voltage VINT may become equal to reference voltage VREF.
FIG. 3 is a circuit diagram showing an example of configuration of the reference voltage generation circuit shown in FIG. 1.
Referring to FIG. 3, reference voltage generation circuit 30 includes output transistor 31 supplied with external power supply voltage VCC for supplying reference voltage VREF to raised voltage power supply circuit 10 and lowered voltage power supply circuit 20 which serves as a load, differential amplifier circuit 32 supplied with raised voltage VP for outputting a control voltage for controlling the gate voltage of output transistor 31, and phase compensation capacitor CP interposed between an output contact of differential amplifier circuit 32 and the ground potential for preventing oscillation. Differential amplifier circuit 32 has a configuration similar to that of differential amplifier circuit 22 for the lowered voltage power supply circuit shown in FIG. 2.
Comparison voltage VR supplied from comparison voltage generation circuit 40 is input to non-inverted input terminal 33 of differential amplifier circuit 32. Reference voltage VREF output from differential amplifier circuit 32 through output transistor 31 is divided by trimming resistors R3, R4, and feedback voltage VREFxe2x80x2 which increases in proportion to reference voltage VREF is fed back to inverted input terminal 34 of differential amplifier circuit 32.
Where raised voltage power supply circuit 10 has such a configuration as shown in FIG. 1, it utilizes reference voltage VREF output from reference voltage generation circuit 30 to produce raised voltage VP, and reference voltage generation circuit 30 uses raised voltage VP output from raised voltage power supply circuit 10 to produce reference voltage VREF. Therefore, even if external power supply voltage VCC is supplied, reference voltage VREF and raised voltage VP are not output. Accordingly, startup circuit 35 for starting up reference voltage generation circuit 30 when external power supply voltage VCC is turned on is connected to reference voltage generation circuit 30.
Startup circuit 35 includes output transistor 36 formed from a P-channel MOSFET supplied with external power supply voltage VCC, and differential amplifier circuit 37 supplied with external power supply voltage VCC for outputting a control voltage for controlling the gate voltage of output transistor 36. Comparison voltage VR is input to inverted input terminal 38 of differential amplifier circuit 37, and reference voltage VREF divided by trimming resistors R3, R4 is fed back to non-inverted input terminal 39 of differential amplifier circuit 37.
Differential amplifier circuit 37 includes transistors Q31, Q32 formed from P-channel MOSFETs connected commonly at the gates thereof, transistors Q33, Q34 formed from N-channel MOSFETs connected in series to transistors Q31, Q32 and connected commonly at the sources thereof, and constant current source 50 to supplying predetermined current to transistors Q31 to Q34.
Transistors Q31, Q32 form a current mirror circuit by connection of the gate and the drain of transistor Q31 and operate so that the values of current flowing between the source-drain of transistors Q31, Q32 may be equal to each other. The gate of output transistor 36 is connected to the drain of transistor Q33.
Transistors (N-channel MOSFETs) Q33, Q34 connected to inverted input terminal 38 and non-inverted input terminal 39, respectively, are formed with transistor sizes different from each other, and differential amplifier circuit 37 operates so that the voltage fed back to non-inverted input terminal 39 may be a little lower (by approximately 0.1 V) than comparison voltage VR input to inverted input terminal 38.
In reference voltage generation circuit 30 having the configuration described above, voltage VREFxe2x80x2 obtained by division of the output voltage (reference voltage VREF) by means of trimming resistors R3, R4 is fed back to inverted input terminal 34 of differential amplifier circuit 32, and such reference voltage VREF which depends upon comparison voltage VR input to non-inverted input terminal 33 and the resistance ratio between trimming resistors R3, R4 as given by the following expression (1) is output from output transistor 31:
VREF=VRxc3x97(R3+R4)/R4xe2x80x83xe2x80x83(1)
Since startup circuit 35 raises the output voltage to (VRxe2x88x920.1 [V])xc3x97(R3+R4)/R4 when the external power supply is turned on, also raised voltage VP produced by utilization of reference voltage VREF rises to a certain level. Accordingly, differential amplifier circuit 32 of reference voltage generation circuit 30 operates and raises its output voltage to a predetermined voltage (reference voltage VREF).
Startup circuit 35 oscillates upon starting up because it does not have phase compensation capacitor CP. If the output voltage of startup circuit 35 reaches the predetermined voltage, then the voltage fed back to non-inverted input terminal 39 (node D) of differential amplifier circuit 37 becomes substantially equal to comparison voltage VR. Since differential amplifier circuit 37 has an input offset voltage (approximately 0.1 V) through the differentiation in transistor size of transistors Q33, Q34 as described above, the voltage at the output contact (node C) is fluctuated in the positive direction until it becomes substantially equal to external power supply voltage VCC, whereupon output transistor 36 is turned off and the oscillation of startup circuit 35 stops completely. Provision of such means for stopping the oscillation eliminates an otherwise possible problem even if startup circuit 35 oscillates when the external power supply is turned on, and consequently, the current to be supplied from constant current source 50 can be reduced.
FIG. 4 is a circuit diagram showing an example of configuration of the comparison voltage generation circuit shown in FIG. 1.
Referring to FIG. 4, comparison voltage generation circuit 40 includes two transistors Q41, Q42 formed from N-channel MOSFETs having threshold voltages different from each other and outputs a voltage difference between threshold voltages Vt of two transistors Q41, Q42 as comparison voltage VR.
In comparison voltage generation circuit 40 having the configuration just described, even if threshold voltages Vt of transistors Q41, Q42 are varied by a variation of the ambient temperature, an otherwise possible variation of comparison voltage VR can be suppressed if the sizes of transistors Q41, Q42 and the resistance values of resistors R5, R6 are set so as to cancel the voltage variation.
As described above, in startup circuit 35 provided in reference voltage generation circuit 30 shown in FIG. 3, N-channel MOSFETs Q33, Q34 connected to inverted input terminal 38 and non-inverted input terminal 39 of differential amplifier circuit 37, respectively, are formed with different transistor sizes.
This technique utilizes a well-known short channel effect that threshold voltage Vt drops as gate length Lpoly of a MOSFET decreases. In this instance, two N-channel MOSFETs Q33, Q34 are formed with different gate lengths Lpoly to set their threshold voltage Vt to different values thereby to provide input offset voltage VOF between non-inverted input terminal 39 and inverted input terminal 38 of differential amplifier circuit 37. More particularly, one of the N-channel MOSFETs is formed with a greater channel length than that of the other N-channel MOSFET to provide a difference of approximately 0.1 to 0.2 V between two threshold voltages Vt.
However, in a MOSFET for use with a semiconductor integrated circuit in recent years, further advancement in high integration gives rise to occurrence of such a reverse short channel effect as illustrated in FIG. 5 wherein, as gate length Lpoly, decreases, threshold voltage Vt, rises, but as gate length Lpoly further decreases, threshold voltage Vt drops suddenly.
It is considered that the reverse short channel effect arises from the fact as one of the reasons that, although depending upon the structure of the MOSFET, a point defect is generated by ion implantation into the source-drain region and the point defect and impurity in the proximity of the source-drain region join together and pile up toward the surface of the substrate thereby to increase the impurity density in the proximity of the opposite ends of the channel. Normally, threshold voltage Vt rises as the impurity density of the channel region increases. Accordingly, as the gate length Lpoly decreases, the ratio of the region of the higher impurity density in the proximity of the channel increases due to the pile-up described above, and this raises threshold voltage Vt.
As seen from FIG. 6, although threshold voltage Vt decreases in a region of the Lpolyxe2x88x92Vt characteristic by the reverse short channel effect in which gate length Lpoly is comparatively large, it does not vary very much. Therefore, in order to assure the difference in threshold voltage Vt of approximately 0.1 V, the transistor sizes must be greatly different. On the contrary, in another region wherein gate length Lpoly is small, threshold voltage Vt varies suddenly, and a small manufacturing error of gate length Lpoly appears as a great variation of threshold voltage Vt. This does not stabilize the manufacturing process. Further, the reverse short channel effect relies so much upon the manufacturing process conditions that increase of the gate length sometimes does not result in threshold voltage Vt.
In short, in a semiconductor integrated circuit in recent years, it has become difficult to set the threshold voltages of two N-channel MOSFETs for use with a differential amplifier circuit for a startup circuit so as to provide a predetermined difference between them by making gate length Lpoly of the N-channel MOSFETs different from each other. It is to be noted that, if the difference between threshold voltages Vt is set to a low value, then the operation of the differential amplifier circuit becomes so unstable that there is the possibility that it may oscillate even in a steady state. Accordingly, although the difference between threshold voltages Vt need not be set with a high degree of accuracy, it needs to be set at least to a voltage difference (approximately 0. 1 V) with which the differential amplifier circuit does not oscillate.
It is an object of the present invention to provide a differential amplifier circuit wherein a predetermined input offset voltage can be provided between an inverted input terminal and a non-inverted input terminal with certainty.
In order to attain the object described above, according to the present invention, there is provided a differential amplifier circuit, comprising a first transistor and a second transistor cooperatively forming a current mirror circuit, a third transistor connected in series to the first transistor and connected to an inverted input terminal through which a comparison voltage which is a predetermined constant voltage is input to the third transistor, a fourth transistor connected in series to the second transistor and connected to a non-inverted input terminal through which a feedback voltage which increases in proportion to an output voltage of the third transistor is input to the fourth transistor, a constant current source for supplying-predetermined current to the first, second, third and fourth transistors, and an offset circuit connected in series to the third transistor for providing a predetermined input offset voltage between the inverted input terminal and the non-inverted input terminal.
By forming a differential amplifier circuit having such an offset circuit as described above, an input offset voltage can be provided with certainty between the inverted input terminal and the non-inverted input terminal of the differential amplifier circuit.
Particularly where the differential amplifier circuit of the present invention is applied to a startup circuit for starting up an internal voltage generation circuit when power supply is made available, which does not require setting of the value of an input offset voltage with a high degree of accuracy, even if a MOSFET whose characteristic of the threshold voltage with respect to the gate length is varied by the reverse short channel effect is used to form the differential amplifier circuit, a predetermined input offset voltage can be provided with certainty between the inverted input terminal and the non-inverted input terminal. Accordingly, an internal voltage generation circuit which operates stably can be obtained.
The above and other objects, features, and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings which illustrate examples of the present invention.